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| RF2196 0 RoHS Compliant & Pb-Free Product Typical Applications * 3V CDMA PCS Handsets * 3V CDMA KPCS Handsets * 3V TDMA/GAIT PCS Handsets Product Description The RF2196 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide process, and has been designed for use as the final RF amplifier in 3V CDMA and CDMA2000 handsets as well as other applications in the 1750MHz to 1910MHz band. The RF2196 has a low power mode to extend battery life under low output power conditions. The package is an ultra small 4mmx4mm, 16-pin QFN plastic package with backside ground. 0.10 C B -B- 3V PCS LINEAR POWER AMPLIFIER * 3V CDMA 2000 PCS Handsets * Spread-Spectrum Systems * Portable Battery-Powered Equipment 4.00 0.10 C B 2 PLCS 3.75 2 PLCS 2.00 0.80 TYP 2 A 1.60 2 PLCS 3.75 0.75 0.50 INDEX AREA Dimensions in mm. 1.50 SQ. 4.00 0.10 C A 2 PLCS 0.45 0.28 3.20 2 PLCS 2.00 0.10 C A 2 PLCS Shaded pin is lead 1. 12 MAX 0.05 0.00 0.10 M C A B 1.00 0.90 0.75 0.65 C 0.05 Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Package Style: QFN, 16-Pin, 4x4 Features * Single 3V Supply * 29dBm Linear Output Power * 35% Linear Efficiency RF IN GND NC NC NC * Low Power Mode (Up to 20dBm) * 55mA Idle Current 1 VPD1 2 MODE 3 VPD2 4 5 GND 16 15 14 13 12 VCC1 11 VCC1 10 VCC Ordering Information 6 NC 7 RF OUT 8 RF OUT 9 GND RF2196 3V PCS Linear Power Amplifier RF2196PCBA-41X Fully Assembled Evaluation Board Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A2 060918 2-345 RF2196 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Mode Voltage (VMODE) Control Voltage (VREG) Input RF Power Operating Case Temperature Storage Temperature Rating +8.0 +5.2 +4.2 +3.0 +10 -30 to +110 -30 to +150 Unit VDC VDC VDC VDC dBm C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter High Power State (VMODE Low) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection Input VSWR Output VSWR Noise Power Specification Min. Typ. Max. Unit Condition Case T=25C, VCC =3.4V, VREG =2.85V, VMODE =0V to 0.5V, Freq=1850MHz to 1910MHz (unless otherwise specified) 1850 25 1910 27 -50 -63 29 35 -46 -62 <2:1 MHz dB dBc dBc dBm % dBc dBc POUT =29dBm ACPR@1.25MHz ACPR@2.25MHz No damage. No oscillations. >-70dBc At 80MHz offset. Case T=25C, VCC =3.4V, VREG =2.85V, VMODE =2V to 3V, Freq=1850MHz to 1910MHz (unless otherwise specified) -44 -56 10:1 6:1 -141 dBm/Hz Low Power State (VMODE High) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Max ICC Adjacent Channel Power Rejection Input VSWR Output VSWR 1850 16 1910 20 -45 -60 20 160 <-50 <-60 2:1 MHz dB dBc dBc dBm mA dBc dBc 16 -46 -58 10:1 6:1 POUT =+16dBm (all currents included) ACPR@1.25MHz ACPR@2.25MHz No damage. No oscillations. >-70dBc 2-346 Rev A2 060918 RF2196 Parameter High Power State CDMA 2000 1x (VMODE LOW) Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Pilot+FCH 9600+SCH0 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection 1850 27 26.5 -49 -61 29 -46 -63 1910 MHz dB dBm dBc dBc dBm dBc dBc 2.5dB Backoff included in IS95D 5.4dB peak to average at CCDF of 1% ACPR@1.25MHz ACPR@2.25MHz 4.5dB peak to average at CCDF of 1% ACPR@1.25MHz ACPR@2.25MHz Case T=25C, VCC =3.4V, VREG =2.85V, VMODE =2V to 3V, Freq=1850MHz to 1910MHz Specification Min. Typ. Max. Unit Condition Case T=25C, VCC =3.4V, VREG =2.85V, VMODE =0V to 0.5V, Freq=1850MHz to 1910MHz (unless otherwise specified) Low Power State CDMA 2000 1x (VMODE HIGH) Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection 1850 19 16 20 -52 -65 16 20 -52 -65 1910 MHz dB dBm dBc dBc dBm dBc dBc 4.2 V mA mA mA mA A V V V V 5.4dB peak to average at CCDF of 1% ACPR@1.25MHz ACPR@2.25MHz 4.5dB peak to average at CCDF of 1% ACPR@1.25MHz ACPR@2.25MHz DC Supply Supply Voltage Quiescent Current VREG Current VMODE Current Total Current (Power Down) VREG "Low" Voltage VREG "High" Voltage VMODE "Low" Voltage VMODE "High" Voltage 3.0 3.4 185 55 5 VMODE =Low VMODE =High 0 2.75 0 2.0 2.85 10 1 10 0.5 2.95 0.5 3.0 VREG =Low Rev A2 060918 2-347 RF2196 Pin 1 2 3 4 5 6 Function GND VREG1 MODE VREG2 GND NC Description This pin is internally grounded to the die flag. Power Down control for first stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). For nominal operation (High Gain Mode), VMODE is set LOW. When set HIGH, the driver and final are dynamically scaled to reduce the device size and as a result to reduce idle current. Power Down control for the second stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). Connect to ground plane via 15nH inductor. DC return for the second stage bias circuit. This pin has no internal bonding; therefore, this pin can be connected to output pin 7, connected to the ground plane, or not connected. Slight tuning of the output match may be required due to stray capacitance of the pin. RF output and power supply for final stage. This is the unmatched colRF OUT lector output of the second stage. A DC block is required following the matching components. The biasing may be provided via a parallel L-C set for resonance at the operating frequency of 1710MHz to 1910MHz. From Bias It is important to select an inductor with very low DC resistance with a Network 1A current rating. Alternatively, shunt microstrip techniques are also applicable and provide very low DC resistance. Low frequency bypassing is required for stability. Same as pin 7. See pin 7. This pin is internally grounded to the die flag. Supply for bias reference and control circuits. High frequency bypassing may be necessary. Power supply for first stage and interstage match. Pins 11 and 12 should be connected by a common trace where the pins contact the printed circuit board. Same as pin 11. It is recommended that these pins be connected to the ground plane for improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11 and 12). It is recommended that these pins be connected to the ground plane for improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11 and 12). It is recommended that these pins be connected to the ground plane for improved isolation between RF IN (pin 16) and the VCC1 pins (pins 11 and 12). RF input. An external 15pF series capacitor is required as a DC block. In addition, the matching circuit shown is required to improve input VSWR. Interface Schematic 7 RF OUT 8 9 10 11 12 13 14 15 16 RF OUT GND VCC VCC1 VCC1 NC NC NC RF IN VCC1 15 pF RF IN 3.6 pF GND1 From Bias Stages TL Pkg Base GND Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. 2-348 Rev A2 060918 RF2196 Application Schematic US - CDMA RF IN Matching network for optimum input return loss 15 pF 3.6 pF Bypassing for VREG1 and VREG2 Interstage tuning for centering frequency response RF Choke - Bias inductor for the amplifier interstage TL4 + VREG 1 F Jumper Jumper 1 k 15 pF 1 2 3 4 16 15 14 13 12 11 10 11 pF TL3 10 nF Ferrite 10 Bypassing for VCC VMODE 1 F + VCC 15 pF 15 pF 5 6 7 8 9 Bias return 12 nH Matching network for optimum load impedance 4.7 pF TL2 2.2 pF TL1 2.5 nH 15 pF 2.2 pF 10 nF 4.7 F 15 pF Pins 1 and 9 are internally grounded to the die flag. Transmission Line Length RF OUT CDMA (US) TL1 30 mils TL2 140 mils TL3 15 mils TL4 200 mils Rev A2 060918 2-349 RF2196 Evaluation Board Schematic US - CDMA RF IN C5 15 pF C24 3.6 pF P1 P1 1 P1 1 VCC P2 P1 1 P1 1 VREG P3 TL4 VMODE P4 GND C26 1 uF + P2 R11 Jumper P3 R12 Jumper R1 1 k C27 15 pF 2 3 4 C13 15 pF 1 16 15 14 13 12 11 10 TL3 C30 11 pF L2 Ferrite 10 C8 10 nF C25 + 1 uF P1 C6 15 pF 5 6 7 8 9 L4 12 nH C1** 4.7 pF TL2 C14** 2.2 pF TL1 L1* 2.5 nH C7 2.2 pF C4 15 pF C28 10 nF C2 4.7 uF C3 15 pF Pins 1 and 9 are internally grounded to the die flag. * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). Board CDMA (US) C30 (pF) 11 C1 (pF) 4.7 L1 (nH) 2.5 C14 (pF) 2.2 RF OUT Transmission Line Length CDMA (US) TL1 30 mils TL2 140 mils TL3 15 mils TL4 200 mils 2-350 Rev A2 060918 RF2196 Evaluation Board Layout Board Size 2.0" x 2.0" Board Thickness 0.028"; Board Material FR-4; Multi-Layer; Ground Plane at 0.014" Rev A2 060918 2-351 RF2196 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern A = 0.51 x 0.89 (mm) Typ. B = 0.89 x 0.51 (mm) Typ. C = 1.52 (mm) Sq. 3.20 Typ. 0.81 Typ. Dimensions in mm. Pin 1 A 1.73 Typ. 0.81 Typ. B B 0.94 Typ. A A A A A B C B B B 0.81 Typ. 1.60 Typ. A A A A 1.60 Typ. 1.73 Typ. Figure 1. PCB Metal Land Pattern (Top View) 2-352 Rev A2 060918 RF2196 PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB Metal Land Pattern with a 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. A = 0.71 x 1.09 (mm) Typ. B = 1.09 x 0.71 (mm) Typ. C = 1.73 (mm) Sq. 3.20 Typ. 0.81 Typ. Pin 1 Dimensions in mm. A 1.73 Typ. 0.81 Typ. B B 0.94 Typ. A A A A A B C B B B 0.81 Typ. 1.60 Typ. A A A A 1.60 Typ. 1.73 Typ. Figure 2. PCB Solder Mask (Top View) Thermal Pad and Via Design The PCB metal land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Rev A2 060918 2-353 RF2196 2-354 Rev A2 060918 |
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